Conventionally, when an arithmetic device such as a CPU, an I/O device such as a storage, or the like, accesses data on a main memory, in order to suppress delay to improve transfer speed and to reduce power consumption, a cache memory for temporarily storing data is used. A cache memory is comprised of an SRAM, or the like, which operates at higher speed than a main memory. The CPU, or the like, can perform high speed processing by accessing data stored in the cache memory.
Typically, the cache memory is comprised of a cache line array for temporarily storing data, and a cache tag indicating which region of the main memory is temporarily stored in the cache line array.
Conventionally, the arithmetic device and the I/O device share a single cache memory. Therefore, when the arithmetic device and the I/O device access the main memory at the same time, the cache line array of the cache memory is used at the same time. In such a case, capacity of the cache line array which can be used for the I/O device is reduced. Then, for example, also when data is simply transferred from an input device to a storage device, because data cannot be temporarily held in the cache line array due to small capacity of the cache line array which can be used for the I/O device, it is necessary to access the main memory to read and write data, and, because a cache hit ratio decreases, the transfer speed decreases and power consumption increases.